There is known a delay adjustment circuit in which an upper pass gate is able to output an output signal delaying from an input signal by a basic delay time and a lower pass gate is able to output delaying by a delay time made by adding a fraction of the basic delay time to the basic delay time (for example, see Patent Document 1). A selector selects either one of the upper and lower pass gates based on a digital control signal.
Further, there is known a clock signal control circuit which makes polyphase clock signals that have phase errors influence each other to average phase error components of the respective clock signals while maintaining phases of the respective clock signals (for example, see Patent Document 2).    [Patent Document 1] Japanese Laid-open Patent Publication No. 4-291510    [Patent Document 2] Japanese Laid-open Patent Publication No. 2001-7686